Enums

Enums used in NI-FGEN

nifgen.AnalogPath

AnalogPath.MAIN

Specifies use of the main path. NI-FGEN chooses the amplifier based on the user-specified gain.

AnalogPath.DIRECT

Specifies use of the direct path.

AnalogPath.FIXED_LOW_GAIN

Specifies use of the low-gain amplifier in the main path, no matter what value the user specifies for gain. This setting limits the output range.

AnalogPath.FIXED_HIGH_GAIN

Specifies use of the high-gain amplifier in the main path.

nifgen.BusType

BusType.INVALID

Indicates an invalid bus type.

BusType.AT

Indicates the signal generator is the AT bus type.

BusType.PCI

Indicates the signal generator is the PCI bus type.

BusType.PXI

Indicates the signal generator is the PXI bus type.

BusType.VXI

Indicates the signal generator is the VXI bus type.

BusType.PCMCIA

Indicates the signal generator is the PCI-CMA bus type.

BusType.PXIE

Indicates the signal generator is the PXI Express bus type.

nifgen.ByteOrder

ByteOrder.LITTLE

ByteOrder.BIG

nifgen.ClockMode

ClockMode.HIGH_RESOLUTION

High resolution sampling—Sample rate is generated by a high–resolution clock source.

ClockMode.DIVIDE_DOWN

Divide down sampling—Sample rates are generated by dividing the source frequency.

ClockMode.AUTOMATIC

Automatic Selection—NI-FGEN selects between the divide–down and high–resolution clocking modes.

nifgen.DataMarkerEventLevelPolarity

DataMarkerEventLevelPolarity.HIGH

When the operation is ready to start, the Ready for Start event level is high.

DataMarkerEventLevelPolarity.LOW

When the operation is ready to start, the Ready for Start event level is low.

nifgen.DataProcessingMode

DataProcessingMode.REAL

The waveform data points are real numbers (I data).

DataProcessingMode.COMPLEX

The waveform data points are complex numbers (I/Q data).

nifgen.DoneEventActiveLevel

DoneEventActiveLevel.HIGH

When the operation is ready to start, the Ready for Start event level is high.

DoneEventActiveLevel.LOW

When the operation is ready to start, the Ready for Start event level is low.

nifgen.DoneEventDelayUnits

DoneEventDelayUnits.SAMPLE_CLOCK_PERIODS

Specifies the pulse width in Sample clock periods.

DoneEventDelayUnits.SECONDS

Specifies the pulse width in seconds.

nifgen.DoneEventOutputBehavior

DoneEventOutputBehavior.PULSE

Triggers a pulse for a specified period of time.

DoneEventOutputBehavior.LEVEL

Shifts high or low while the event is active, depending on the active state you specify.

nifgen.DoneEventPulsePolarity

DoneEventPulsePolarity.HIGH

When the operation is ready to start, the Ready for Start event level is high.

DoneEventPulsePolarity.LOW

When the operation is ready to start, the Ready for Start event level is low.

nifgen.DoneEventPulseWidthUnits

DoneEventPulseWidthUnits.SAMPLE_CLOCK_PERIODS

Specifies the pulse width in Sample clock periods.

DoneEventPulseWidthUnits.SECONDS

Specifies the pulse width in seconds.

nifgen.FilterType

FilterType.FLAT

Applies a flat filter to the data with the passband value specified in the nifgen.Session.osp_fir_filter_flat_passband property.

FilterType.RAISED_COSINE

Applies a raised cosine filter to the data with the alpha value specified in the nifgen.Session.osp_fir_filter_raised_cosine_alpha property.

FilterType.ROOT_RAISED_COSINE

Applies a root raised cosine filter to the data with the alpha value specified in the nifgen.Session.osp_fir_filter_root_raised_cosine_alpha property.

FilterType.GAUSSIAN

Applies a Gaussian filter to the data with the BT value specified in the nifgen.Session.osp_fir_filter_gaussian_bt property.

FilterType.CUSTOM

Applies a custom filter to the data. If CUSTOM is selected, you must provide a set of FIR filter coefficients with the nifgen.Session.configure_custom_fir_filter_coefficients() method.

nifgen.HardwareState

HardwareState.IDLE

HardwareState.WAITING_FOR_START_TRIGGER

HardwareState.RUNNING

HardwareState.DONE

HardwareState.HARDWARE_ERROR

nifgen.IdleBehavior

IdleBehavior.HOLD_LAST

While in an Idle or Wait state, the output signal remains at the last voltage generated prior to entering the state.

IdleBehavior.JUMP_TO

While in an Idle or Wait state, the output signal remains at the value configured in the Idle or Wait value property.

nifgen.MarkerEventDelayUnits

MarkerEventDelayUnits.SAMPLE_CLOCK_PERIODS

Specifies the pulse width in Sample clock periods.

MarkerEventDelayUnits.SECONDS

Specifies the pulse width in seconds.

nifgen.MarkerEventOutputBehavior

MarkerEventOutputBehavior.PULSE

Triggers a pulse for a specified period of time.

MarkerEventOutputBehavior.LEVEL

Shifts high or low while the event is active, depending on the active state you specify.

MarkerEventOutputBehavior.TOGGLE

Changes to high or low while the event is active, depending on the active state you specify.

nifgen.MarkerEventPulsePolarity

MarkerEventPulsePolarity.HIGH

When the operation is ready to start, the Ready for Start event level is high.

MarkerEventPulsePolarity.LOW

When the operation is ready to start, the Ready for Start event level is low.

nifgen.MarkerEventPulseWidthUnits

MarkerEventPulseWidthUnits.SAMPLE_CLOCK_PERIODS

Specifies the pulse width in Sample clock periods.

MarkerEventPulseWidthUnits.SECONDS

Specifies the pulse width in seconds.

nifgen.MarkerEventToggleInitialState

MarkerEventToggleInitialState.HIGH

Sets the initial state of the Marker event to high.

MarkerEventToggleInitialState.LOW

Sets the initial state of the Marker event to low.

nifgen.OSPMode

OSPMode.IF

The OSP block generates intermediate frequency (IF) data.

OSPMode.BASEBAND

The OSP block generates baseband data.

nifgen.OSPOverflowErrorReporting

OSPOverflowErrorReporting.ERROR

NI-FGEN returns errors whenever an overflow has occurred in the OSP block.

OSPOverflowErrorReporting.DISABLED

NI-FGEN does not return errors when an overflow occurs in the OSP block.

nifgen.OutputMode

OutputMode.FUNC

Standard Method mode— Generates standard method waveforms such as sine, square, triangle, and so on.

OutputMode.ARB

Arbitrary waveform mode—Generates waveforms from user-created/provided waveform arrays of numeric data.

OutputMode.SEQ

Arbitrary sequence mode — Generates downloaded waveforms in an order your specify.

OutputMode.FREQ_LIST

Frequency List mode—Generates a standard method using a list of frequencies you define.

OutputMode.SCRIPT

Script mode—Allows you to use scripting to link and loop multiple waveforms in complex combinations.

nifgen.ReadyForStartEventActiveLevel

ReadyForStartEventActiveLevel.HIGH

When the operation is ready to start, the Ready for Start event level is high.

ReadyForStartEventActiveLevel.LOW

When the operation is ready to start, the Ready for Start event level is low.

nifgen.ReferenceClockSource

ReferenceClockSource.CLOCK_IN

Specifies that the CLK IN input signal from the front panel connector is used as the Reference Clock source.

ReferenceClockSource.NONE

Specifies that a Reference Clock is not used.

ReferenceClockSource.ONBOARD_REFERENCE_CLOCK

Specifies that the onboard Reference Clock is used as the Reference Clock source.

ReferenceClockSource.PXI_CLOCK

Specifies the PXI Clock is used as the Reference Clock source.

ReferenceClockSource.RTSI_7

Specifies that the RTSI line 7 is used as the Reference Clock source.

nifgen.RelativeTo

RelativeTo.START

RelativeTo.CURRENT

nifgen.SampleClockSource

SampleClockSource.CLOCK_IN

Specifies that the signal at the CLK IN front panel connector is used as the Sample Clock source.

SampleClockSource.DDC_CLOCK_IN

Specifies that the Sample Clock from DDC connector is used as the Sample Clock source.

SampleClockSource.ONBOARD_CLOCK

Specifies that the onboard clock is used as the Sample Clock source.

SampleClockSource.PXI_STAR_LINE

Specifies that the PXI_STAR trigger line is used as the Sample Clock source.

SampleClockSource.PXI_TRIGGER_LINE_0RTSI_0

Specifies that the PXI or RTSI line 0 is used as the Sample Clock source.

SampleClockSource.PXI_TRIGGER_LINE_1RTSI_1

Specifies that the PXI or RTSI line 1 is used as the Sample Clock source.

SampleClockSource.PXI_TRIGGER_LINE_2RTSI_2

Specifies that the PXI or RTSI line 2 is used as the Sample Clock source.

SampleClockSource.PXI_TRIGGER_LINE_3RTSI_3

Specifies that the PXI or RTSI line 3 is used as the Sample Clock source.

SampleClockSource.PXI_TRIGGER_LINE_4RTSI_4

Specifies that the PXI or RTSI line 4 is used as the Sample Clock source.

SampleClockSource.PXI_TRIGGER_LINE_5RTSI_5

Specifies that the PXI or RTSI line 5 is used as the Sample Clock source.

SampleClockSource.PXI_TRIGGER_LINE_6RTSI_6

Specifies that the PXI or RTSI line 6 is used as the Sample Clock source.

SampleClockSource.PXI_TRIGGER_LINE_7RTSI_7

Specifies that the PXI or RTSI line 7 is used as the Sample Clock source.

nifgen.SampleClockTimebaseSource

SampleClockTimebaseSource.CLOCK_IN

Specifies that the external signal on the CLK IN front panel connector is used as the source.

SampleClockTimebaseSource.ONBOARD_CLOCK

Specifies that the onboard Sample Clock timebase is used as the source.

nifgen.ScriptTriggerDigitalEdgeEdge

ScriptTriggerDigitalEdgeEdge.RISING

Rising Edge

ScriptTriggerDigitalEdgeEdge.FALLING

Falling Edge

nifgen.ScriptTriggerDigitalLevelActiveLevel

ScriptTriggerDigitalLevelActiveLevel.HIGH

High Level

ScriptTriggerDigitalLevelActiveLevel.LOW

Low Level

nifgen.ScriptTriggerType

ScriptTriggerType.TRIG_NONE

No trigger is configured. Signal generation starts immediately.

ScriptTriggerType.DIGITAL_EDGE

Trigger is asserted when a digital edge is detected.

ScriptTriggerType.DIGITAL_LEVEL

Trigger is asserted when a digital level is detected.

ScriptTriggerType.SOFTWARE_EDGE

Trigger is asserted when a software edge is detected.

nifgen.Signal

Signal.ONBOARD_REFERENCE_CLOCK

Signal.SYNC_OUT

Signal.START_TRIGGER

Signal.MARKER_EVENT

Signal.SAMPLE_CLOCK_TIMEBASE

Signal.SYNCHRONIZATION

Signal.SAMPLE_CLOCK

Signal.REFERENCE_CLOCK

Signal.SCRIPT_TRIGGER

Signal.READY_FOR_START_EVENT

Signal.STARTED_EVENT

Signal.DONE_EVENT

Signal.DATA_MARKER_EVENT

nifgen.StartTriggerDigitalEdgeEdge

StartTriggerDigitalEdgeEdge.RISING

Rising Edge

StartTriggerDigitalEdgeEdge.FALLING

Falling Edge

nifgen.StartTriggerType

StartTriggerType.TRIG_NONE

None

StartTriggerType.DIGITAL_EDGE

Digital Edge

StartTriggerType.SOFTWARE_EDGE

Software Edge

StartTriggerType.P2P_ENDPOINT_FULLNESS

P2P Endpoint Fullness

nifgen.StartedEventActiveLevel

StartedEventActiveLevel.HIGH

When the operation is ready to start, the Ready for Start event level is high.

StartedEventActiveLevel.LOW

When the operation is ready to start, the Ready for Start event level is low.

nifgen.StartedEventDelayUnits

StartedEventDelayUnits.SAMPLE_CLOCK_PERIODS

Specifies the pulse width in Sample clock periods.

StartedEventDelayUnits.SECONDS

Specifies the pulse width in seconds.

nifgen.StartedEventOutputBehavior

StartedEventOutputBehavior.PULSE

Triggers a pulse for a specified period of time.

StartedEventOutputBehavior.LEVEL

Shifts high or low while the event is active, depending on the active state you specify.

nifgen.StartedEventPulsePolarity

StartedEventPulsePolarity.HIGH

When the operation is ready to start, the Ready for Start event level is high.

StartedEventPulsePolarity.LOW

When the operation is ready to start, the Ready for Start event level is low.

nifgen.StartedEventPulseWidthUnits

StartedEventPulseWidthUnits.SAMPLE_CLOCK_PERIODS

Specifies the pulse width in Sample clock periods.

StartedEventPulseWidthUnits.SECONDS

Specifies the pulse width in seconds.

nifgen.SynchronizationSource

SynchronizationSource.TTL0

PXI TRIG0 or VXI TTL0

SynchronizationSource.TTL1

PXI TRIG1 or VXI TTL1

SynchronizationSource.TTL2

PXI TRIG2 or VXI TTL2

SynchronizationSource.TTL3

PXI TRIG3 or VXI TTL3

SynchronizationSource.TTL4

PXI TRIG4 or VXI TTL4

SynchronizationSource.TTL5

PXI TRIG5 or VXI TTL5

SynchronizationSource.TTL6

PXI TRIG6 or VXI TTL6

SynchronizationSource.RTSI_0

RTSI 0

SynchronizationSource.RTSI_1

RTSI 1

SynchronizationSource.RTSI_2

RTSI 2

SynchronizationSource.RTSI_3

RTSI 3

SynchronizationSource.RTSI_4

RTSI 4

SynchronizationSource.RTSI_5

RTSI 5

SynchronizationSource.RTSI_6

RTSI 6

SynchronizationSource.NONE

No Synchronization Source

nifgen.TerminalConfiguration

TerminalConfiguration.SINGLE_ENDED

Single-ended operation

TerminalConfiguration.DIFFERENTIAL

Differential operation

nifgen.Trigger

Trigger.START

Trigger.SCRIPT

nifgen.TriggerMode

TriggerMode.SINGLE

Single Trigger Mode - The waveform you describe in the sequence list is generated only once by going through the entire staging list. Only one trigger is required to start the waveform generation. You can use Single trigger mode with the output mode in any mode. After a trigger is received, the waveform generation starts from the first stage and continues through to the last stage. Then, the last stage generates repeatedly until you stop the waveform generation.

TriggerMode.CONTINUOUS

Continuous Trigger Mode - The waveform you describe in the staging list generates infinitely by repeatedly cycling through the staging list. After a trigger is received, the waveform generation starts from the first stage and continues through to the last stage. After the last stage completes, the waveform generation loops back to the start of the first stage and continues until it is stopped. Only one trigger is required to start the waveform generation.

TriggerMode.STEPPED

Stepped Trigger Mode - After a start trigger is received, the waveform described by the first stage generates. Then, the device waits for the next trigger signal. On the next trigger, the waveform described by the second stage generates, and so on. After the staging list completes, the waveform generation returns to the first stage and continues in a cyclic fashion. After any stage has generated completely, the first eight samples of the next stage are repeated continuously until the next trigger is received. trigger mode.

Note

In Frequency List mode, Stepped trigger mode is the same as Burst

TriggerMode.BURST

Burst Trigger Mode - After a start trigger is received, the waveform described by the first stage generates until another trigger is received. At the next trigger, the buffer of the previous stage completes, and then the waveform described by the second stage generates. After the staging list completes, the waveform generation returns to the first stage and continues in a cyclic fashion. In Frequency List mode, the duration instruction is ignored, and the trigger switches the frequency to the next frequency in the list. trigger mode.

Note

In Frequency List mode, Stepped trigger mode is the same as Burst

nifgen.TriggerSource

TriggerSource.IMMEDIATE

Immediate-The signal generator does not wait for a trigger of any kind.

TriggerSource.EXTERNAL

External-The signal generator waits for a trigger on the external trigger input

TriggerSource.SOFTWARE_TRIG

Software Trigger-The signal generator waits until you call nifgen.Session.SendSWTrigger().

TriggerSource.TTL0

PXI TRIG0 or VXI TTL0

TriggerSource.TTL1

PXI TRIG1 or VXI TTL1

TriggerSource.TTL2

PXI TRIG2 or VXI TTL2

TriggerSource.TTL3

PXI TRIG3 or VXI TTL3

TriggerSource.TTL4

PXI TRIG4 or VXI TTL4

TriggerSource.TTL5

PXI TRIG5 or VXI TTL5

TriggerSource.TTL6

PXI TRIG6 or VXI TTL6

TriggerSource.PXI_STAR

PXI star

TriggerSource.RTSI_0

RTSI line 0

TriggerSource.RTSI_1

RTSI line 1

TriggerSource.RTSI_2

RTSI line 2

TriggerSource.RTSI_3

RTSI line 3

TriggerSource.RTSI_4

RTSI line 4

TriggerSource.RTSI_5

RTSI line 5

TriggerSource.RTSI_6

RTSI line 6

TriggerSource.RTSI_7

RTSI line 7

TriggerSource.PFI_0

PFI 0

TriggerSource.PFI_1

PFI 1

TriggerSource.PFI_2

PFI 2

TriggerSource.PFI_3

PFI 3

TriggerSource.OTHER_TERMINAL

Specifies that another terminal is used.

nifgen.TriggerWhen

TriggerWhen.HIGH

TriggerWhen.LOW

nifgen.VideoWaveformType

VideoWaveformType.PAL_B

PAL B Video Type

VideoWaveformType.PAL_D

PAL D Video Type

VideoWaveformType.PAL_G

PAL G Video Type

VideoWaveformType.PAL_H

PAL H Video Type

VideoWaveformType.PAL_I

PAL I Video Type

VideoWaveformType.PAL_M

PAL M Video Type

VideoWaveformType.PAL_N

PAL N Video Type

VideoWaveformType.NTSC_M

NTSC M Video Type

nifgen.WaitBehavior

WaitBehavior.HOLD_LAST

While in an Idle or Wait state, the output signal remains at the last voltage generated prior to entering the state.

WaitBehavior.JUMP_TO

While in an Idle or Wait state, the output signal remains at the value configured in the Idle or Wait value property.

nifgen.Waveform

Waveform.SINE

Sinusoid waveform

Waveform.SQUARE

Square waveform

Waveform.TRIANGLE

Triange waveform

Waveform.RAMP_UP

Positive ramp waveform

Waveform.RAMP_DOWN

Negative ramp waveform

Waveform.DC

Constant voltage

Waveform.NOISE

White noise

Waveform.USER

User-defined waveform as defined by the nifgen.Session.define_user_standard_waveform() method.