Enums

Enums used in NI-FGEN

AnalogPath

class nifgen.AnalogPath[source]
MAIN

Specifies use of the main path. NI-FGEN chooses the amplifier based on the user-specified gain.

DIRECT

Specifies use of the direct path.

FIXED_LOW_GAIN

Specifies use of the low-gain amplifier in the main path, no matter what value the user specifies for gain. This setting limits the output range.

FIXED_HIGH_GAIN

Specifies use of the high-gain amplifier in the main path.

BusType

class nifgen.BusType[source]
INVALID

Indicates an invalid bus type.

AT

Indicates the signal generator is the AT bus type.

PCI

Indicates the signal generator is the PCI bus type.

PXI

Indicates the signal generator is the PXI bus type.

VXI

Indicates the signal generator is the VXI bus type.

PCMCIA

Indicates the signal generator is the PCI-CMA bus type.

PXIE

Indicates the signal generator is the PXI Express bus type.

ByteOrder

class nifgen.ByteOrder[source]
LITTLE
BIG

ClockMode

class nifgen.ClockMode[source]
HIGH_RESOLUTION

High resolution sampling—Sample rate is generated by a high–resolution clock source.

DIVIDE_DOWN

Divide down sampling—Sample rates are generated by dividing the source frequency.

AUTOMATIC

Automatic Selection—NI-FGEN selects between the divide–down and high–resolution clocking modes.

DataMarkerEventLevelPolarity

class nifgen.DataMarkerEventLevelPolarity[source]
HIGH

When the operation is ready to start, the Ready for Start event level is high.

LOW

When the operation is ready to start, the Ready for Start event level is low.

HardwareState

class nifgen.HardwareState[source]
IDLE
WAITING_FOR_START_TRIGGER
RUNNING
DONE
HARDWARE_ERROR

IdleBehavior

class nifgen.IdleBehavior[source]
HOLD_LAST

While in an Idle or Wait state, the output signal remains at the last voltage generated prior to entering the state.

JUMP_TO

While in an Idle or Wait state, the output signal remains at the value configured in the Idle or Wait value property.

OutputMode

class nifgen.OutputMode[source]
FUNC

Standard Method mode— Generates standard method waveforms such as sine, square, triangle, and so on.

ARB

Arbitrary waveform mode—Generates waveforms from user-created/provided waveform arrays of numeric data.

SEQ

Arbitrary sequence mode — Generates downloaded waveforms in an order your specify.

FREQ_LIST

Frequency List mode—Generates a standard method using a list of frequencies you define.

SCRIPT

Script mode—Allows you to use scripting to link and loop multiple waveforms in complex combinations.

ReferenceClockSource

class nifgen.ReferenceClockSource[source]
CLOCK_IN

Specifies that the CLK IN input signal from the front panel connector is used as the Reference Clock source.

NONE

Specifies that a Reference Clock is not used.

ONBOARD_REFERENCE_CLOCK

Specifies that the onboard Reference Clock is used as the Reference Clock source.

PXI_CLOCK

Specifies the PXI Clock is used as the Reference Clock source.

RTSI_7

Specifies that the RTSI line 7 is used as the Reference Clock source.

RelativeTo

class nifgen.RelativeTo[source]
START
CURRENT

SampleClockSource

class nifgen.SampleClockSource[source]
CLOCK_IN

Specifies that the signal at the CLK IN front panel connector is used as the Sample Clock source.

DDC_CLOCK_IN

Specifies that the Sample Clock from DDC connector is used as the Sample Clock source.

ONBOARD_CLOCK

Specifies that the onboard clock is used as the Sample Clock source.

PXI_STAR_LINE

Specifies that the PXI_STAR trigger line is used as the Sample Clock source.

PXI_TRIGGER_LINE_0_RTSI_0

Specifies that the PXI or RTSI line 0 is used as the Sample Clock source.

PXI_TRIGGER_LINE_1_RTSI_1

Specifies that the PXI or RTSI line 1 is used as the Sample Clock source.

PXI_TRIGGER_LINE_2_RTSI_2

Specifies that the PXI or RTSI line 2 is used as the Sample Clock source.

PXI_TRIGGER_LINE_3_RTSI_3

Specifies that the PXI or RTSI line 3 is used as the Sample Clock source.

PXI_TRIGGER_LINE_4_RTSI_4

Specifies that the PXI or RTSI line 4 is used as the Sample Clock source.

PXI_TRIGGER_LINE_5_RTSI_5

Specifies that the PXI or RTSI line 5 is used as the Sample Clock source.

PXI_TRIGGER_LINE_6_RTSI_6

Specifies that the PXI or RTSI line 6 is used as the Sample Clock source.

PXI_TRIGGER_LINE_7_RTSI_7

Specifies that the PXI or RTSI line 7 is used as the Sample Clock source.

SampleClockTimebaseSource

class nifgen.SampleClockTimebaseSource[source]
CLOCK_IN

Specifies that the external signal on the CLK IN front panel connector is used as the source.

ONBOARD_CLOCK

Specifies that the onboard Sample Clock timebase is used as the source.

ScriptTriggerDigitalEdgeEdge

class nifgen.ScriptTriggerDigitalEdgeEdge[source]
RISING

Rising Edge

FALLING

Falling Edge

ScriptTriggerType

class nifgen.ScriptTriggerType[source]
TRIG_NONE

No trigger is configured. Signal generation starts immediately.

DIGITAL_EDGE

Trigger is asserted when a digital edge is detected.

DIGITAL_LEVEL

Trigger is asserted when a digital level is detected.

SOFTWARE_EDGE

Trigger is asserted when a software edge is detected.

StartTriggerDigitalEdgeEdge

class nifgen.StartTriggerDigitalEdgeEdge[source]
RISING

Rising Edge

FALLING

Falling Edge

StartTriggerType

class nifgen.StartTriggerType[source]
TRIG_NONE

None

DIGITAL_EDGE

Digital Edge

SOFTWARE_EDGE

Software Edge

P2P_ENDPOINT_FULLNESS

P2P Endpoint Fullness

TerminalConfiguration

class nifgen.TerminalConfiguration[source]
SINGLE_ENDED

Single-ended operation

DIFFERENTIAL

Differential operation

TriggerMode

class nifgen.TriggerMode[source]
SINGLE

Single Trigger Mode - The waveform you describe in the sequence list is generated only once by going through the entire staging list. Only one trigger is required to start the waveform generation. You can use Single trigger mode with the output mode in any mode. After a trigger is received, the waveform generation starts from the first stage and continues through to the last stage. Then, the last stage generates repeatedly until you stop the waveform generation.

CONTINUOUS

Continuous Trigger Mode - The waveform you describe in the staging list generates infinitely by repeatedly cycling through the staging list. After a trigger is received, the waveform generation starts from the first stage and continues through to the last stage. After the last stage completes, the waveform generation loops back to the start of the first stage and continues until it is stopped. Only one trigger is required to start the waveform generation.

STEPPED

Stepped Trigger Mode - After a start trigger is received, the waveform described by the first stage generates. Then, the device waits for the next trigger signal. On the next trigger, the waveform described by the second stage generates, and so on. After the staging list completes, the waveform generation returns to the first stage and continues in a cyclic fashion. After any stage has generated completely, the first eight samples of the next stage are repeated continuously until the next trigger is received. trigger mode.

Note

In Frequency List mode, Stepped trigger mode is the same as Burst

BURST

Burst Trigger Mode - After a start trigger is received, the waveform described by the first stage generates until another trigger is received. At the next trigger, the buffer of the previous stage completes, and then the waveform described by the second stage generates. After the staging list completes, the waveform generation returns to the first stage and continues in a cyclic fashion. In Frequency List mode, the duration instruction is ignored, and the trigger switches the frequency to the next frequency in the list. trigger mode.

Note

In Frequency List mode, Stepped trigger mode is the same as Burst

WaitBehavior

class nifgen.WaitBehavior[source]
HOLD_LAST

While in an Idle or Wait state, the output signal remains at the last voltage generated prior to entering the state.

JUMP_TO

While in an Idle or Wait state, the output signal remains at the value configured in the Idle or Wait value property.

Waveform

class nifgen.Waveform[source]
SINE

Sinusoid waveform

SQUARE

Square waveform

TRIANGLE

Triange waveform

RAMP_UP

Positive ramp waveform

RAMP_DOWN

Negative ramp waveform

DC

Constant voltage

NOISE

White noise

USER

User-defined waveform as defined by the nifgen.Session.define_user_standard_waveform() method.