Enums¶

Enums used in NI-FGEN

AnalogPath¶

class nifgen.AnalogPath¶

MAIN¶: Specifies use of the main path. NI-FGEN chooses the amplifier based on the user-specified gain.

DIRECT¶: Specifies use of the direct path.

FIXED_LOW_GAIN¶: Specifies use of the low-gain amplifier in the main path, no matter what value the user specifies for gain. This setting limits the output range.

FIXED_HIGH_GAIN¶: Specifies use of the high-gain amplifier in the main path.

BusType¶

class nifgen.BusType¶

INVALID¶: Indicates an invalid bus type.

AT¶: Indicates the signal generator is the AT bus type.

PCI¶: Indicates the signal generator is the PCI bus type.

PXI¶: Indicates the signal generator is the PXI bus type.

VXI¶: Indicates the signal generator is the VXI bus type.

PCMCIA¶: Indicates the signal generator is the PCI-CMA bus type.

PXIE¶: Indicates the signal generator is the PXI Express bus type.

ByteOrder¶

class nifgen.ByteOrder¶

LITTLE¶

BIG¶

ClockMode¶

class nifgen.ClockMode¶

HIGH_RESOLUTION¶: High resolution sampling—Sample rate is generated by a high–resolution clock source.

DIVIDE_DOWN¶: Divide down sampling—Sample rates are generated by dividing the source frequency.

AUTOMATIC¶: Automatic Selection—NI-FGEN selects between the divide–down and high–resolution clocking modes.

DataMarkerEventLevelPolarity¶

class nifgen.DataMarkerEventLevelPolarity¶

HIGH¶: When the operation is ready to start, the Ready for Start event level is high.

LOW¶: When the operation is ready to start, the Ready for Start event level is low.

DataProcessingMode¶

class nifgen.DataProcessingMode¶

REAL¶: The waveform data points are real numbers (I data).

COMPLEX¶: The waveform data points are complex numbers (I/Q data).

DoneEventActiveLevel¶

class nifgen.DoneEventActiveLevel¶

HIGH¶: When the operation is ready to start, the Ready for Start event level is high.

LOW¶: When the operation is ready to start, the Ready for Start event level is low.

DoneEventDelayUnits¶

class nifgen.DoneEventDelayUnits¶

SAMPLE_CLOCK_PERIODS¶: Specifies the pulse width in Sample clock periods.

SECONDS¶: Specifies the pulse width in seconds.

DoneEventOutputBehavior¶

class nifgen.DoneEventOutputBehavior¶

PULSE¶: Triggers a pulse for a specified period of time.

LEVEL¶: Shifts high or low while the event is active, depending on the active state you specify.

DoneEventPulsePolarity¶

class nifgen.DoneEventPulsePolarity¶

HIGH¶: When the operation is ready to start, the Ready for Start event level is high.

LOW¶: When the operation is ready to start, the Ready for Start event level is low.

DoneEventPulseWidthUnits¶

class nifgen.DoneEventPulseWidthUnits¶

SAMPLE_CLOCK_PERIODS¶: Specifies the pulse width in Sample clock periods.

SECONDS¶: Specifies the pulse width in seconds.

FilterType¶

class nifgen.FilterType¶

FLAT¶: Applies a flat filter to the data with the passband value specified in the nifgen.Session.osp_fir_filter_flat_passband property.

RAISED_COSINE¶: Applies a raised cosine filter to the data with the alpha value specified in the nifgen.Session.osp_fir_filter_raised_cosine_alpha property.

ROOT_RAISED_COSINE¶: Applies a root raised cosine filter to the data with the alpha value specified in the nifgen.Session.osp_fir_filter_root_raised_cosine_alpha property.

GAUSSIAN¶: Applies a Gaussian filter to the data with the BT value specified in the nifgen.Session.osp_fir_filter_gaussian_bt property.

CUSTOM¶: Applies a custom filter to the data. If CUSTOM is selected, you must provide a set of FIR filter coefficients with the nifgen.Session.configure_custom_fir_filter_coefficients() method.

HardwareState¶

class nifgen.HardwareState¶

IDLE¶

WAITING_FOR_START_TRIGGER¶

RUNNING¶

DONE¶

HARDWARE_ERROR¶

IdleBehavior¶

class nifgen.IdleBehavior¶

HOLD_LAST¶: While in an Idle or Wait state, the output signal remains at the last voltage generated prior to entering the state.

JUMP_TO¶: While in an Idle or Wait state, the output signal remains at the value configured in the Idle or Wait value property.

MarkerEventDelayUnits¶

class nifgen.MarkerEventDelayUnits¶

SAMPLE_CLOCK_PERIODS¶: Specifies the pulse width in Sample clock periods.

SECONDS¶: Specifies the pulse width in seconds.

MarkerEventOutputBehavior¶

class nifgen.MarkerEventOutputBehavior¶

PULSE¶: Triggers a pulse for a specified period of time.

LEVEL¶: Shifts high or low while the event is active, depending on the active state you specify.

TOGGLE¶: Changes to high or low while the event is active, depending on the active state you specify.

MarkerEventPulsePolarity¶

class nifgen.MarkerEventPulsePolarity¶

HIGH¶: When the operation is ready to start, the Ready for Start event level is high.

LOW¶: When the operation is ready to start, the Ready for Start event level is low.

MarkerEventPulseWidthUnits¶

class nifgen.MarkerEventPulseWidthUnits¶

SAMPLE_CLOCK_PERIODS¶: Specifies the pulse width in Sample clock periods.

SECONDS¶: Specifies the pulse width in seconds.

MarkerEventToggleInitialState¶

class nifgen.MarkerEventToggleInitialState¶

HIGH¶: Sets the initial state of the Marker event to high.

LOW¶: Sets the initial state of the Marker event to low.

OSPMode¶

class nifgen.OSPMode¶

IF¶: The OSP block generates intermediate frequency (IF) data.

BASEBAND¶: The OSP block generates baseband data.

OSPOverflowErrorReporting¶

class nifgen.OSPOverflowErrorReporting¶

ERROR¶: NI-FGEN returns errors whenever an overflow has occurred in the OSP block.

DISABLED¶: NI-FGEN does not return errors when an overflow occurs in the OSP block.

OutputMode¶

class nifgen.OutputMode¶

FUNC¶: Standard Method mode— Generates standard method waveforms such as sine, square, triangle, and so on.

ARB¶: Arbitrary waveform mode—Generates waveforms from user-created/provided waveform arrays of numeric data.

SEQ¶: Arbitrary sequence mode — Generates downloaded waveforms in an order your specify.

FREQ_LIST¶: Frequency List mode—Generates a standard method using a list of frequencies you define.

SCRIPT¶: Script mode—Allows you to use scripting to link and loop multiple waveforms in complex combinations.

ReadyForStartEventActiveLevel¶

class nifgen.ReadyForStartEventActiveLevel¶

HIGH¶: When the operation is ready to start, the Ready for Start event level is high.

LOW¶: When the operation is ready to start, the Ready for Start event level is low.

ReferenceClockSource¶

class nifgen.ReferenceClockSource¶

CLOCK_IN¶: Specifies that the CLK IN input signal from the front panel connector is used as the Reference Clock source.

NONE¶: Specifies that a Reference Clock is not used.

ONBOARD_REFERENCE_CLOCK¶: Specifies that the onboard Reference Clock is used as the Reference Clock source.

PXI_CLOCK¶: Specifies the PXI Clock is used as the Reference Clock source.

RTSI_7¶: Specifies that the RTSI line 7 is used as the Reference Clock source.

RelativeTo¶

class nifgen.RelativeTo¶

START¶

CURRENT¶

SampleClockSource¶

class nifgen.SampleClockSource¶

CLOCK_IN¶: Specifies that the signal at the CLK IN front panel connector is used as the Sample Clock source.

DDC_CLOCK_IN¶: Specifies that the Sample Clock from DDC connector is used as the Sample Clock source.

ONBOARD_CLOCK¶: Specifies that the onboard clock is used as the Sample Clock source.

PXI_STAR_LINE¶: Specifies that the PXI_STAR trigger line is used as the Sample Clock source.

PXI_TRIGGER_LINE_0RTSI_0¶: Specifies that the PXI or RTSI line 0 is used as the Sample Clock source.

PXI_TRIGGER_LINE_1RTSI_1¶: Specifies that the PXI or RTSI line 1 is used as the Sample Clock source.

PXI_TRIGGER_LINE_2RTSI_2¶: Specifies that the PXI or RTSI line 2 is used as the Sample Clock source.

PXI_TRIGGER_LINE_3RTSI_3¶: Specifies that the PXI or RTSI line 3 is used as the Sample Clock source.

PXI_TRIGGER_LINE_4RTSI_4¶: Specifies that the PXI or RTSI line 4 is used as the Sample Clock source.

PXI_TRIGGER_LINE_5RTSI_5¶: Specifies that the PXI or RTSI line 5 is used as the Sample Clock source.

PXI_TRIGGER_LINE_6RTSI_6¶: Specifies that the PXI or RTSI line 6 is used as the Sample Clock source.

PXI_TRIGGER_LINE_7RTSI_7¶: Specifies that the PXI or RTSI line 7 is used as the Sample Clock source.

SampleClockTimebaseSource¶

class nifgen.SampleClockTimebaseSource¶

CLOCK_IN¶: Specifies that the external signal on the CLK IN front panel connector is used as the source.

ONBOARD_CLOCK¶: Specifies that the onboard Sample Clock timebase is used as the source.

ScriptTriggerDigitalEdgeEdge¶

class nifgen.ScriptTriggerDigitalEdgeEdge¶

RISING¶: Rising Edge

FALLING¶: Falling Edge

ScriptTriggerDigitalLevelActiveLevel¶

class nifgen.ScriptTriggerDigitalLevelActiveLevel¶

HIGH¶: High Level

LOW¶: Low Level

ScriptTriggerType¶

class nifgen.ScriptTriggerType¶

TRIG_NONE¶: No trigger is configured. Signal generation starts immediately.

DIGITAL_EDGE¶: Trigger is asserted when a digital edge is detected.

DIGITAL_LEVEL¶: Trigger is asserted when a digital level is detected.

SOFTWARE_EDGE¶: Trigger is asserted when a software edge is detected.

StartTriggerDigitalEdgeEdge¶

class nifgen.StartTriggerDigitalEdgeEdge¶

RISING¶: Rising Edge

FALLING¶: Falling Edge

StartTriggerType¶

class nifgen.StartTriggerType¶

TRIG_NONE¶: None

DIGITAL_EDGE¶: Digital Edge

SOFTWARE_EDGE¶: Software Edge

P2P_ENDPOINT_FULLNESS¶: P2P Endpoint Fullness

StartedEventActiveLevel¶

class nifgen.StartedEventActiveLevel¶

HIGH¶: When the operation is ready to start, the Ready for Start event level is high.

LOW¶: When the operation is ready to start, the Ready for Start event level is low.

StartedEventDelayUnits¶

class nifgen.StartedEventDelayUnits¶

SAMPLE_CLOCK_PERIODS¶: Specifies the pulse width in Sample clock periods.

SECONDS¶: Specifies the pulse width in seconds.

StartedEventOutputBehavior¶

class nifgen.StartedEventOutputBehavior¶

PULSE¶: Triggers a pulse for a specified period of time.

LEVEL¶: Shifts high or low while the event is active, depending on the active state you specify.

StartedEventPulsePolarity¶

class nifgen.StartedEventPulsePolarity¶

HIGH¶: When the operation is ready to start, the Ready for Start event level is high.

LOW¶: When the operation is ready to start, the Ready for Start event level is low.

StartedEventPulseWidthUnits¶

class nifgen.StartedEventPulseWidthUnits¶

SAMPLE_CLOCK_PERIODS¶: Specifies the pulse width in Sample clock periods.

SECONDS¶: Specifies the pulse width in seconds.

SynchronizationSource¶

class nifgen.SynchronizationSource¶

TTL0¶: PXI TRIG0 or VXI TTL0

TTL1¶: PXI TRIG1 or VXI TTL1

TTL2¶: PXI TRIG2 or VXI TTL2

TTL3¶: PXI TRIG3 or VXI TTL3

TTL4¶: PXI TRIG4 or VXI TTL4

TTL5¶: PXI TRIG5 or VXI TTL5

TTL6¶: PXI TRIG6 or VXI TTL6

RTSI_0¶: RTSI 0

RTSI_1¶: RTSI 1

RTSI_2¶: RTSI 2

RTSI_3¶: RTSI 3

RTSI_4¶: RTSI 4

RTSI_5¶: RTSI 5

RTSI_6¶: RTSI 6

NONE¶: No Synchronization Source

TerminalConfiguration¶

class nifgen.TerminalConfiguration¶

SINGLE_ENDED¶: Single-ended operation

DIFFERENTIAL¶: Differential operation

Trigger¶

class nifgen.Trigger¶

START¶

SCRIPT¶

TriggerMode¶

class nifgen.TriggerMode¶

SINGLE¶: Single Trigger Mode - The waveform you describe in the sequence list is generated only once by going through the entire staging list. Only one trigger is required to start the waveform generation. You can use Single trigger mode with the output mode in any mode. After a trigger is received, the waveform generation starts from the first stage and continues through to the last stage. Then, the last stage generates repeatedly until you stop the waveform generation.

CONTINUOUS¶: Continuous Trigger Mode - The waveform you describe in the staging list generates infinitely by repeatedly cycling through the staging list. After a trigger is received, the waveform generation starts from the first stage and continues through to the last stage. After the last stage completes, the waveform generation loops back to the start of the first stage and continues until it is stopped. Only one trigger is required to start the waveform generation.

STEPPED¶: Stepped Trigger Mode - After a start trigger is received, the waveform described by the first stage generates. Then, the device waits for the next trigger signal. On the next trigger, the waveform described by the second stage generates, and so on. After the staging list completes, the waveform generation returns to the first stage and continues in a cyclic fashion. After any stage has generated completely, the first eight samples of the next stage are repeated continuously until the next trigger is received. trigger mode.

Note

In Frequency List mode, Stepped trigger mode is the same as Burst

BURST¶: Burst Trigger Mode - After a start trigger is received, the waveform described by the first stage generates until another trigger is received. At the next trigger, the buffer of the previous stage completes, and then the waveform described by the second stage generates. After the staging list completes, the waveform generation returns to the first stage and continues in a cyclic fashion. In Frequency List mode, the duration instruction is ignored, and the trigger switches the frequency to the next frequency in the list. trigger mode.

Note

In Frequency List mode, Stepped trigger mode is the same as Burst

TriggerSource¶

class nifgen.TriggerSource¶

IMMEDIATE¶: Immediate-The signal generator does not wait for a trigger of any kind.

EXTERNAL¶: External-The signal generator waits for a trigger on the external trigger input

SOFTWARE_TRIG¶: Software Trigger-The signal generator waits until you call nifgen.Session.SendSWTrigger().

TTL0¶: PXI TRIG0 or VXI TTL0

TTL1¶: PXI TRIG1 or VXI TTL1

TTL2¶: PXI TRIG2 or VXI TTL2

TTL3¶: PXI TRIG3 or VXI TTL3

TTL4¶: PXI TRIG4 or VXI TTL4

TTL5¶: PXI TRIG5 or VXI TTL5

TTL6¶: PXI TRIG6 or VXI TTL6

PXI_STAR¶: PXI star

RTSI_0¶: RTSI line 0

RTSI_1¶: RTSI line 1

RTSI_2¶: RTSI line 2

RTSI_3¶: RTSI line 3

RTSI_4¶: RTSI line 4

RTSI_5¶: RTSI line 5

RTSI_6¶: RTSI line 6

RTSI_7¶: RTSI line 7

PFI_0¶: PFI 0

PFI_1¶: PFI 1

PFI_2¶: PFI 2

PFI_3¶: PFI 3

OTHER_TERMINAL¶: Specifies that another terminal is used.

TriggerWhen¶

class nifgen.TriggerWhen¶

HIGH¶

LOW¶

VideoWaveformType¶

class nifgen.VideoWaveformType¶

PAL_B¶: PAL B Video Type

PAL_D¶: PAL D Video Type

PAL_G¶: PAL G Video Type

PAL_H¶: PAL H Video Type

PAL_I¶: PAL I Video Type

PAL_M¶: PAL M Video Type

PAL_N¶: PAL N Video Type

NTSC_M¶: NTSC M Video Type

WaitBehavior¶

class nifgen.WaitBehavior¶

HOLD_LAST¶: While in an Idle or Wait state, the output signal remains at the last voltage generated prior to entering the state.

JUMP_TO¶: While in an Idle or Wait state, the output signal remains at the value configured in the Idle or Wait value property.

Waveform¶

class nifgen.Waveform¶

SINE¶: Sinusoid waveform

SQUARE¶: Square waveform

TRIANGLE¶: Triange waveform

RAMP_UP¶: Positive ramp waveform

RAMP_DOWN¶: Negative ramp waveform

DC¶: Constant voltage

NOISE¶: White noise

USER¶: User-defined waveform as defined by the nifgen.Session.define_user_standard_waveform() method.